Bench Probing Plan

The LSI board (PCB 20918) is exposed with the top cover removed, its 8–9 test points accessible without tilting any keyboards. Before Phase 1 bench testing (CapSense viability), a systematic probing session characterizes the organ’s existing signals — frequencies, voltage levels, impedances, and timing. These measurements establish the baseline that every subsequent design decision builds on.

Equipment

Tool	Specs	Role
20 MHz oscilloscope	Analog bandwidth 20 MHz	Voltage measurement, waveform shape, analog signals
8-ch USB logic analyzer	Saleae-compatible, 24 MHz sampling, 5.25V max input	Digital timing, frequency measurement, multi-channel capture
NanoVNA-H	Vector network analyzer, USB-controlled via mcnanovna	Bus bar impedance, filter network characterization, S-parameters
sigrok + PulseView	Open source, Linux	Logic analyzer software with frequency counters and protocol decoders

Voltage Safety — Read This First

The logic analyzer will be damaged by direct connection to most organ signals.

• Key contact bus bars carry 0–12V square waves (confirmed in signal architecture)
• TOS supply voltage: 15V typical (MK50240 datasheet specifies V_SS = 11–16V)
• Logic analyzer absolute max input: 5.25V

Rule: The oscilloscope measures voltage on every signal FIRST. The logic analyzer only touches signals confirmed ≤ 5V.

For signals above 5V, a resistive voltage divider on a solderless breadboard scales them down safely:

Target	Divider	Output at 12V in	Output at 15V in
3.3V from 12V	10kΩ + 3.9kΩ	3.37V	4.21V
3.45V from 15V	8.2kΩ + 3.3kΩ	3.44V	4.30V

Signal bandwidth is in the kHz range — divider parasitic capacitance is irrelevant at these frequencies.

TOS Master Clock — Expected Frequency

The confirmed 142164X (AY-3-0214 family, 16-pin DIP, see IC identification) uses a crystal-controlled master clock. From the MK50240 datasheet:

Master clock: 2.000240 MHz

This is the only signal near the logic analyzer’s Nyquist limit. At 24 MHz sampling, each clock cycle gets roughly 12 samples — adequate for frequency measurement but not for clean waveform reconstruction. The 20 MHz oscilloscope will show it, but attenuated (~−3 dB at its bandwidth limit). Use a 10× probe to minimize loading.

Every other signal in the organ is orders of magnitude lower in frequency and will be massively oversampled.

TOS Output Frequencies

The MK50240 divides the 2.000240 MHz master clock by integer divisors to produce the top octave — the 13 chromatic notes from which all lower octaves are derived by binary division. These are the frequencies the logic analyzer should confirm:

Pin	Note	Divisor	Frequency (Hz)	Samples/Cycle at 24 MHz
15	C (high)	239	8,369	2,868
14	B	253	7,906	3,034
13	A♯	268	7,463	3,216
12	A	284	7,043	3,409
11	G♯	301	6,645	3,613
10	G	319	6,271	3,830
9	F♯	338	5,918	4,055
8	F	358	5,588	4,295
7	E	379	5,278	4,548
6	D♯	402	4,976	4,823
5	D	426	4,695	5,112
4	C♯	451	4,435	5,413
16	C (low)	478	4,185	5,735

All TOS outputs fall between 4–8.4 kHz — massively oversampled by the 24 MHz logic analyzer. Frequency measurement will be extremely accurate.

Divider Chain Frequencies

Each divider stage halves the frequency. The logic analyzer covers every octave with increasing ease as frequency drops:

Octave	Frequency Range	Example (A)	Logic Analyzer Coverage
TOS output (top)	4,185–8,369 Hz	7,043 Hz	Excellent
÷2	2,093–4,185 Hz	3,520 Hz	Excellent
÷4	1,047–2,093 Hz	1,760 Hz	Excellent
÷8	523–1,047 Hz	880 Hz	Excellent
÷16	262–523 Hz	440 Hz (A4)	Excellent
÷32	131–262 Hz	220 Hz	Excellent
÷64 (pedals)	65–131 Hz	110 Hz	Excellent
÷128 (lowest pedal)	33–65 Hz	55 Hz	Excellent

Probing Sequence

Session 1: Oscilloscope Only — Voltage Characterization

Safety-critical. Organ powered on, 10× probe, no logic analyzer connected.

1. Measure voltage on each of the 8–9 test points on PCB 20918

   Document DC level, AC amplitude, and waveform shape for each. These test points were put there by Wurlitzer’s engineers — they almost certainly correspond to key signal nodes in the divider-keyer chain.

2. Measure voltage on a key contact bus bar

   Press and hold a key while probing the corresponding bus bar. Confirm the 0–12V swing documented in the signal architecture. Record the exact high and low levels — the divider resistor values depend on this.

3. Measure TOS output voltage

   If accessible from the test points, verify the TOS output amplitude. The MK50240 datasheet specifies output levels relative to V_SS, which may be 15V.

4. Measure master clock amplitude at the TOS clock input pin

   Use 10× probe to minimize loading on the 2 MHz crystal oscillator circuit. Record amplitude and waveform shape (sine vs. square — crystal oscillators in this era could go either way).

5. Document the safe/unsafe signal map

   Classify each probed point: ≤ 5V (safe for logic analyzer direct connection) or > 5V (requires voltage divider). This map governs every subsequent session.

Session 2: Logic Analyzer — Digital Signal Characterization

Only after Session 1 confirms voltage levels.

1. Connect to test points confirmed ≤ 5V (or through voltage dividers for higher-voltage signals)

2. Capture TOS outputs — verify all 13 notes present at expected frequencies

   Use PulseView’s frequency counter decoder on each channel. Compare measured frequencies against the table above. Any deviation from the calculated values indicates a master clock frequency error or a different TOS variant than expected.

3. Capture divider chain outputs for one note — verify octave relationships

   Each stage should produce exactly half the frequency of the stage above. Deviations indicate a faulty divider stage.

4. Capture key contact state changes — press/release timing, debounce characteristics

   This feeds directly into the debounce measurement protocol below.

5. Capture multiple keys simultaneously — verify no crosstalk

   Press keys on adjacent bus bars and verify clean, independent transitions with no coupling between channels.

Session 3: Oscilloscope — Analog Signals

1. Leslie reed switch coil drive voltage

   Measure in both Slow and Fast positions. This voltage determines the relay or optocoupler specification for the MIDI Leslie control interface.

2. Expression pedal analog signal

   Sweep the pedal through its full range. Record voltage endpoints and linearity. Check the lateral slide axis separately.

3. Voicing filter outputs

   Capture waveform shapes for flute, reed, and string voices on the oscilloscope. These are the raw filter responses that transform square waves into the organ’s characteristic timbres — worth documenting even though they aren’t directly relevant to the MIDI conversion.

4. Power supply ripple

   Measure ripple on the main DC rails under load (organ playing). This establishes a baseline before the electrolytic recap.

Session 4: NanoVNA — Impedance Characterization

With the organ powered off, the NanoVNA characterizes passive network properties that the oscilloscope and logic analyzer can’t measure directly.

1. Bus bar impedance

   Measure the impedance looking into a bus bar with all keys released (open) and with one key pressed (loaded). The impedance at audio frequencies determines the AC coupling pickup design — specifically, how much signal a capacitively-coupled sensor can extract without loading the bus bar enough to affect the organ’s voicing.

2. Voicing filter network response

   Sweep the filter boards across the audio band (20 Hz – 20 kHz). The S₂₁ (transmission) measurement shows the filter’s frequency response directly, confirming which harmonics each voice tab passes or attenuates. Compare flute (mostly fundamental) vs. string (rich harmonics) vs. reed (nasal bandpass).

3. Expression pedal potentiometer characterization

   Measure resistance and impedance across the pedal’s travel. If the pot is logarithmic vs. linear, the VNA sweep will show it clearly in the impedance-vs-position curve.

4. Key contact impedance

   With a key pressed, measure the contact impedance at the bus bar. Low contact impedance confirms healthy contacts; elevated or inconsistent impedance across keys may indicate oxidized contacts requiring cleaning.

Tip

The NanoVNA is USB-controlled via the mcnanovna MCP server — sweeps, calibration, and data export can be driven directly from the workbench without touching the instrument’s front panel. Export S-parameter data as Touchstone (.s2p) files for documentation and later analysis.

PulseView / sigrok Setup

Install on Arch Linux:

sudo pacman -S sigrok-cli pulseview

Connect the Saleae-compatible analyzer via USB. Sampling rate recommendations:

Measurement	Sampling Rate	Rationale
TOS frequency measurement	12 MHz	6 MHz would suffice; lower rate = longer capture buffer
Divider chain verification	4 MHz	Signals are all < 10 kHz
Key debounce timing	24 MHz	Need µs-scale resolution to see contact bounce

Use the frequency counter decoder on each channel for automated frequency readout. Export captures as .sr files for the project archive.

Key Contact Debounce Measurement

Patent US3330916 describes beryllium-copper + silver-platinum contacts in Wurlitzer organs of this era. Moro’s thesis measured approximately 200 µs oscillation period and 5 ms total settling on Hammond contacts — but the 555’s contacts are a different metallurgy, different geometry, and different spring tension. This measurement establishes the actual debounce timing for the shift register firmware.

Method:

Logic analyzer on a key contact bus bar (through voltage divider if needed), 24 MHz sampling, trigger on falling edge, 10 ms capture window.

1. Press the key slowly, then quickly. Repeat 20 times for statistical significance.

2. Record for each keystroke:

   • First contact to stable closure (total bounce duration)
   • Oscillation period during bounce
   • Any asymmetry between make and break
   • Variation across slow vs. fast keystrokes

3. Repeat on 3–4 keys at different positions across the keyboard (low end, middle, high end) to check for position-dependent variation.

The resulting bounce duration directly determines the debounce delay constant in the ESP32 firmware (Phase 2 of the implementation roadmap). Moro’s 5 ms settling time is the starting assumption — the bench measurement either confirms it or gives us the real number.

What to Record

For each measurement session, document:

• Date, ambient temperature (capacitor ESR and contact resistance both vary with temperature)
• Which test point / pin / bus bar was probed
• Oscilloscope or logic analyzer settings (timebase, voltage scale, sampling rate)
• Screenshot or capture file (.sr for PulseView, .s2p for NanoVNA)
• Measured value vs. expected value from the tables above

Store all capture files in the project repository under captures/ with filenames that encode the session, date, and signal measured.

References

• MK50240 datasheet — clock frequency, pin assignments, divider ratios
• Electric Druid: Adventures in Top Octave Generation — TOS architecture overview
• Signal Architecture — the 555’s internal signal flow
• IC Identification — confirmed chip part numbers on PCB 20918
• Console Disassembly — LSI board location and test points
• Leslie Control — Remaining Investigation — coil voltage measurement needed from Session 3
• Implementation Roadmap — Phase 0 and Phase 1 depend on these measurements
• mcnanovna — MCP server for NanoVNA-H USB control