Simulations
Sim 1 — AC Coupling Feasibility
Section titled “Sim 1 — AC Coupling Feasibility”The fundamental question: does the coupling capacitance between a pickup electrode and the 555’s contact rail change enough with key position to produce a measurable signal?
This simulation sweeps the coupling capacitance from 0.5 pF (key fully up, ~5 mm air gap) through 5 pF (key fully down, ~0.5 mm gap) and measures the resulting voltage at the pickup node. The 555’s TOD divider output — a 440 Hz square wave at 12 V peak — drives the contact rail. A 1 MW load resistor models the PSoC ADC input impedance.
The result: even at the minimum 0.5 pF coupling, the pickup signal is above the noise floor. At 5 pF, the signal reaches hundreds of millivolts peak-to-peak — well within the CY8C29466’s 14-bit ADC range. The physics works.
Sim 2 — Frequency Separation
Section titled “Sim 2 — Frequency Separation”If Approach B uses the organ’s own divider signals as per-key excitation, neighboring notes must be separable by filtering. This simulation tests whether a bandpass filter tuned to one note can reject the adjacent semitone.
The critical finding: passive LC filters with realistic Q factors (20–50) cannot achieve sufficient rejection between semitones — the frequency ratio of a semitone (1.0595:1) is simply too narrow. Active filters with Q > 100 can separate adjacent notes, but require per-key tuning and are impractical at scale.
This drives the architecture toward per-key pickup electrodes rather than shared pickups with frequency demultiplexing. Each key gets its own dedicated sensor, and the filtering requirement drops to rejecting notes an octave or more away — easily achievable with modest Q values.
Sim 3 — Full Detection Chain
Section titled “Sim 3 — Full Detection Chain”The complete signal path from contact rail to ADC readout: AC coupling through the variable air-gap capacitance, bandpass filtering at the note frequency, envelope detection, and sampling. This simulation validates that the chain produces a usable digital reading within the latency budget.
Key results at 1 pF nominal coupling (mid-travel key position):
| Parameter | Result |
|---|---|
| Peak envelope voltage | 119 mV per pF of coupling |
| ADC counts (14-bit, 3.3 V ref) | ~423 counts per pF |
| Envelope settling time | < 3 ms |
The 423 ADC counts per picofarad of coupling change gives roughly 10-bit effective resolution over the key’s travel range — enough for velocity extraction and coarse position tracking, though marginal for fine aftertouch. The < 3 ms settling time fits comfortably within the 5 ms latency budget.
Cross-References
Section titled “Cross-References”- CapSense Feasibility — the sensing approaches these simulations validate
- Prior Art & Thesis Research — research context and design targets
- Analog Block Architecture — PSoC analog block analysis
- Implementation Roadmap — where the simulation results feed into the build plan
- Leslie Motor Simulations — TRIAC and VFD motor control simulations for the Leslie tremolo unit
- Approach — the ESP32 + shift register architecture that the expression layer augments