Analog Block Architecture

The CapSense feasibility overview identifies the CY8C29466’s programmable analog blocks as a key enabler for Approach B — using the organ’s own divider signals as per-key excitation sources. This page unpacks the analog block architecture that makes a small number of PSoC1 chips viable for sensing all 151 keys.

Analog Block Multiplexing

The CY8C29466 contains 12 analog PSoC blocks arranged in a 4-column × 3-row interconnect matrix. Each block can be independently configured as a switched-capacitor filter stage, amplifier, comparator, or DAC by writing a handful of configuration registers — topology, center frequency coefficients, gain, and routing. The crucial property is that those registers can be rewritten mid-operation. A register write takes one or two instruction cycles at 24 MHz, and the block begins operating in its new configuration on the next clock edge. The entire personality of the analog front-end can change in under a microsecond.

This transforms the chip from “12 fixed-function blocks” into a time-division multiplexed signal processor.

Time-Division Frequency Hopping

A single bandpass filter chain — two or three analog blocks cascaded for a second- or third-order response — can serve all ~20 keys assigned to one chip by retuning between samples. On tick 1 the filter’s center frequency registers are set to 440 Hz (A4); the filter settles, the ADC takes a sample, and the amplitude is stored. On tick 2 the same physical blocks retune to 466 Hz (B♭4), settle, sample, store. Twenty channels at 50–100 μs per channel completes a full scan in 1–2 ms — well within the 5 ms latency budget established by Moro’s design targets.

The alternative would be to instantiate 20 parallel bandpass filters, one per key. That would exhaust the 12 analog blocks on a single channel group and still leave no room for the envelope detector or gain stage. Multiplexing is not an optimization — it is the only feasible topology.

Adaptive Sensing Modes

Runtime reconfiguration is not limited to center frequency. The same register-rewrite mechanism supports mode changes that adapt the sensing strategy per-channel based on the key’s current state.

A channel whose key is at rest can be scanned with a wide passband — faster settling, coarser frequency resolution, sufficient for detecting the onset of motion. Once the key state machine transitions to “Press in Progress,” the filter narrows to track amplitude precisely during the critical velocity-extraction window. A pedalboard key that only needs threshold crossing (no velocity) can have its analog block reconfigured from bandpass filter to comparator, eliminating the envelope detection stage entirely and freeing that scan slot’s time budget. Gain staging adapts similarly: weakly coupled keys (longer air gap, thinner pickup trace) get higher gain; keys adjacent to strong emitters get reduced gain to avoid saturation.

The key insight is that each scan slot is not just a frequency selection — it is a complete analog front-end personality, chosen to match what that particular key needs at that particular moment.

Drift Compensation

The 555’s master oscillator is an analog RC circuit — not crystal-locked. It drifts with temperature over the course of a session, and the entire TOD divider chain drifts with it. If the bandpass filters are tuned to nominal frequencies at power-on, a warm afternoon could shift the actual tone generator output far enough that the filters’ passbands no longer center on the signal.

Runtime reconfiguration turns this from a fatal flaw into a solved problem. One scan slot in each cycle can be dedicated to a calibration sweep: the filter tunes across a narrow range around the expected frequency for a reference key, measures amplitude at each step, and identifies the actual peak. The offset between expected and measured center frequency gives the master oscillator’s current drift. Since every note in the TOD chain is derived from the same master clock by integer division, a single drift measurement characterizes the entire instrument. The bandpass center frequencies for all 151 channels are then updated by the same ratio.

The sensing system tunes itself to the organ in real time — the CY8C29466’s analog blocks track the 555’s analog heart beat for beat.

Settling Time Considerations

There is a hard constraint on how fast the frequency hopping can run. A switched-capacitor bandpass filter needs approximately Q / f_center seconds to reach steady-state amplitude after a configuration change. At Q = 30 and f_center = 440 Hz, that is roughly 68 ms — far too slow for a 50 μs scan slot. At Q = 10 the settling drops to about 23 ms, still marginal for the lowest bass notes but workable in the mid-range where most playing occurs.

The Cypress PSoC1 Technical Reference Manual documents a mitigation: pre-charging the filter’s internal capacitors to their expected steady-state voltages before switching the configuration registers. This eliminates the initial transient and allows the filter to begin tracking the input signal within a few clock cycles rather than waiting for the natural envelope to build. Combined with a reduced-Q operating point, the scan slot budget of 50–100 μs becomes achievable across the full frequency range.

Q	f_center	Natural settling	With pre-charge	Scan viable?
30	440 Hz	~68 ms	~1–5 ms	No — still too slow
10	440 Hz	~23 ms	< 100 μs	Yes
10	131 Hz (C3)	~76 ms	< 100 μs	Yes, with pre-charge
10	27.5 Hz (A0 pedal)	~364 ms	~200 μs	Marginal — may need 2 slots

The trade-off is rejection bandwidth: Q = 10 at 440 Hz gives a 3 dB bandwidth of 44 Hz, which means adjacent semitones (A4 at 440 Hz vs. B♭4 at 466 Hz, a 26 Hz gap) are only partially rejected by the filter alone. This is exactly where Sim 2’s finding becomes architecturally load-bearing.

External Mux Expansion

The analysis above assumes a direct connection between each pickup electrode and a PSoC analog input pin — one channel per pin. The 28-pin CY8C29466-24SXI package constrains that to roughly 8 analog input pins: 4 on Port 0 routed through the internal AMUX bus to the analog column inputs, and 4 on Port 2 connected directly to switched-capacitor block inputs. The ~20 channel figure used throughout Approach B comes from the CSD user module’s software multiplexing across these pins (some digital-capable pins can be repurposed for analog in certain configurations, but the core analog routing is limited to these 8). That limitation is what drives the 8-chip estimate for 151 keys — but it assumes no external signal routing.

External analog multiplexers placed between the pickup electrodes and those 8 analog input pins add a second dimension to the scan matrix. The CD74HC4067 (TI SCHS206C) is well-suited here: a 16:1 analog mux in the HC logic family with 70 Ω on-resistance at 5 V supply, 89 MHz bandwidth (orders of magnitude above the 4 kHz signal ceiling), break-before-make switching that prevents charge dump transients between channels, and −75 dB channel-to-channel crosstalk. Each mux requires 4 shared address lines (binary channel select) plus 1 individual enable pin. The older CD4067B (4000-series CMOS, TI SCHS052D) has the same pinout and function but presents ~470 Ω R_ON at 5 V — workable for the relatively high-impedance PSoC analog inputs, but the HC variant is preferred when resolving millivolt-level coupled signals where unnecessary series resistance degrades SNR.

The scaling arithmetic is straightforward. Eight muxes — one per analog input pin — give each chip access to 128 channels. Ten muxes (splitting two analog pins into a second bank) reach 160, enough to cover the full 151-key instrument on a single chip in principle.

Configuration	Muxes per chip	Channels per chip	Chips for 151 keys	GPIO for mux control
No external mux	0	~20	8	0
8 × CD74HC4067 (16:1)	8	128	2	4 shared addr + 8 enable = 12
10 × CD74HC4067 (16:1)	10	160	1	4 shared addr + 10 enable = 14

The single-chip configuration is appealing on paper but runs into the decimator bottleneck. The CY8C29466 has 4 analog columns that can run independent PGA, filter, and comparator chains in parallel — four channels can settle simultaneously, and pipelined settling hides mux switching latency effectively. But the chip has only a single hardware decimator for ADC conversion. All four columns share it, so actual analog-to-digital conversion is serial regardless of how many channels are settling in parallel. At 8-bit resolution with a fast decimator clock, each conversion takes approximately 50–100 μs.

For 151 channels on one chip: 151 × 100 μs = 15.1 ms per full scan — three times the 5 ms latency budget. Two chips at ~75 channels each bring that to 7.5 ms — still marginal. Three chips at ~50 channels each: 5.0 ms, right on the design target extracted from Moro’s work.

This is where the comparator-mode optimization from Adaptive Sensing Modes becomes load-bearing. Not every channel needs a full ADC conversion on every scan cycle. Keys at rest can be scanned in comparator mode — the analog block reconfigured as a threshold detector that trips when the coupled signal exceeds a baseline, bypassing the decimator entirely. Only channels where the comparator has tripped (key in motion) get promoted to full ADC measurement for amplitude tracking and velocity extraction.

In a typical playing scenario, the vast majority of keys are idle at any given moment. If 100 of 151 channels are at rest and scanned via comparator, only ~50 need ADC time: 50 × 100 μs = 5.0 ms on a single chip. The external mux architecture combined with adaptive sensing modes makes a 2-chip solution realistic for the full 151-key instrument — with a single chip achievable under light playing loads.

The GPIO budget is tight but feasible. The 28-pin package provides roughly 14 digital GPIO pins after the analog inputs, XTAL oscillator pins, and power/ground are allocated. A 2-chip architecture with ~5 muxes per chip needs 4 shared address lines plus 5 individual enable lines = 9 GPIO dedicated to mux control, leaving 5 GPIO for SPI or UART communication with the ESP32 — enough for a full-duplex SPI bus (MOSI, MISO, SCK, CS) with one pin to spare for an interrupt line signaling scan completion.

The CY8C20236A Angle

The CY8C20236A’s CSD hardware is designed to measure capacitance, not AC signal amplitude. But its sigma-delta modulator is fundamentally a charge integrator — if the charge injected from the coupled AC signal modulates the integration, the raw CSD counts would reflect the coupling amplitude. This is speculative and would need bench testing, but the hardware might work as an AC amplitude detector without firmware modification of the measurement loop.

The CY8C29466 is the safer bet for Approach B — its programmable analog blocks and 14-bit ADC can straightforwardly implement bandpass → envelope → sample.

References

Cypress / Infineon Application Notes

AN85951 — PSoC 4 and PSoC 6 MCU CapSense Design Guide. Covers shielding, noise immunity, PCB layout, and SmartSense auto-tuning. infineon.com
AN92239 — Proximity Sensing with CapSense. Extends CSD measurement to longer-range detection. infineon.com

Datasheets

CY8C20xx6A — CapSense controller family datasheet. infineon.com
CY8C29466-24SXI — PSoC1 family datasheet. infineon.com